AMD's 2nm Venice server chips are already shipping

> AMD's sixth-generation EPYC chips — codenamed Venice — are reportedly shipping to customers, running on TSMC's 2nm process. The SP7 server processors, sold as the EPYC 9006 series, are said to be the first high-performance computing silicon to reach production on that node. Shipments reportedly started on November 10, 2026, built on AMD's Zen 6 architecture and topping out at 256 cores and 512 threads.

The chips push memory bandwidth as high as 1.6 TB/s and support PCIe 6.0, aimed at dense agentic AI, cloud, HPC and everyday enterprise workloads. Hardware partners aren't waiting around: major OEMs and ODMs have already started shipping systems built on Venice, and Azure and Oracle are expected to roll out Venice-based cloud instances soon.

AMD says more than 240 server platforms are committed to the architecture — a 20% jump over the Turin generation. The shipping SP7 socket handles the high end, while an enterprise-focused SP8 socket lands in the first half of 2027 for mainstream business servers. A separate Venice-X design brings 3D V-Cache for HPC, stacking memory on the chip so hot data sits next to the cores, and Verano covers lower-power LPDDR setups.

The Venice ramp began earlier in 2026 in Taiwan, with AMD eyeing future expansion at TSMC's Arizona fab. There's money behind the push: AMD's data center segment revenue climbed 97% year over year in Q3 2026, hitting a record $8.5 billion on demand for EPYC processors and Instinct GPUs. Venice lands in the same server budgets Intel's Xeon and Nvidia's Vera are chasing.