Archgen unwraps AI agent that hunts down and fixes chip design flaws solo

Archgen Labs is betting chip designers want to stop babysitting error logs. The Y Combinator startup launched an autonomous agent that reads design run reports, flags the critical problems and applies fixes by itself, then loops back to check whether the patch held or spawned new ones. The agent was initially called Newton.

It goes after the usual suspects: timing violations, where signals land too late to keep a chip in sync, and design rule check failures, where a layout breaks the physical rules a foundry demands. According to the company's materials, the agent spans the physical design flow from synthesis, where logic becomes real circuit components, through signoff, the last verification before manufacturing.

Archgen says the agent leans on root-cause analysis and what it calls persistent learning, so it traces why a problem appeared instead of just patching symptoms, and carries those lessons into later runs.

The agent isn't arriving alone. Archgen also built a GPU-accelerated placement engine that decides where big blocks of circuitry sit on a chip, and it took first place in the Hudson River Trading and Partcl macro-placement challenge in June 2026. The second tool, LayerTherm, handles thermal simulation and reportedly runs roughly 5,000 times faster than traditional EDA benchmarks for the job.

Founded in 2026 by CEO Hariharan Ayappane and CTO Naveen Venkat, Archgen is also working with GlobalFoundries on a 3D chip, with the pair targeting a first tapeout in April 2027. Its public launch activities ran from November 6 to 9, 2026.

The cleanup work the agent targets isn't a rounding error. Traditional chip design workflows can stretch up to 18 months, and a big chunk of that time disappears into the same iterative fix-and-recheck cycle Archgen wants to hand off to software.